The present invention relates to a method for manufacturing a semiconductor substrate and, more particularly, to a method for manufacturing a semiconductor substrate on which a high performance, silicon-on-insulator (SOI) transistor and a normal bulk transistor can be formed together.
As the level of semiconductor device integration increases, transistors having submicron channels are continuously being developed. In general, when the channel length of a bulk transistor decreases, various transistor performance properties degrade. Major examples of these performance property degradations include short-channel effects which lead to significant variations in the transistor threshold voltage depending on changes in channel length, and impaired driving capability for the transistor due to hot-carrier effects which occur around the drain junction. To overcome these problems, various drain structures, such as lightly doped drains (LDD) or double implanted LDDs (DI-LDDs), have been widely used. Other techniques which form a channel region having an appropriately adjusted impurity concentration distribution have similarly been used.
There is also an increasing tendency in contemporary semiconductor devices to lower the operating voltage, for example, from 5.0 V to 3.0 V or less. This reduction in operating voltage improves power dissipation and reliability in highly integrated semiconductor devices, but has adverse effects relative to the use of the remedial channel and drain structures previously discussed. For example, in order to obtain desirable transistor characteristics at lower operating voltages, transistor threshold voltages should be less than 0.5 V. This reduction in threshold voltages necessitates a decrease in the impurity concentration of channel regions. The decrease in the impurity concentration in the channel region leads to a significant increase in transistor subthreshold leakage current. In order to achieve the required low threshold voltage and constrain excessive flow of subthreshold leakage current, the subthreshold swing (hereinafter, referred to as S.S.) must be kept small. S.S. is defined as the gate voltage necessary for a ten-fold increase or a ten-fold decrease in drain current at the threshold voltage or below. S.S. can be expressed as EQU S.S..ident.1n[dV.sub.g /d(1nI.sub.ds)] EQU .apprxeq.(kT/q)1n(1+C.sub.d /C.sub.ox)
wherein k equals Boltzman's constant of 1.38.times.10.sup.-23 J/K, T is the absolute temperature, q is electrical charge of 1.60.times.10.sup.-19 C, C.sub.d is the depletion capacitance, and C.sub.ox is the gate oxide capacitance.
As can be seen from the above equation, the value of S.S. can be reduced by increasing the gate oxide capacitance or reducing the depletion capacitance. To achieve this result, the gate insulating film should be thin, or the impurity concentrations around the source and drain junction and around the channel region should be low. However, in the case of a bulk transistor, the degree to which impurity concentrations around the source and drain junction can be reduced is limited. Thus, SOI transistors having lower source and drain junction capacitances have been used as a way around the foregoing problem.
U.S. Pat. No. 4,889,829 describes a method for manufacturing a semiconductor substrate on which a bulk transistor and a SOI transistor may be formed together, though its principle object is not to provide a semiconductor substrate for fabricating a low voltage semiconductor device. FIG. 1 is a cross-sectional view of a semiconductor substrate manufactured according the method disclosed in U.S. Pat. No. 4,889,829.
Referring to FIG. 1, reference numeral 300 denotes a substrate area in which a bulk transistor is formed, and reference numeral 400 denotes a substrate area upon which a SOI transistor is formed. Reference numeral 121 denotes a lower semiconductor substrate. Reference numerals 122 and 124 denote a thermal oxide layer formed over the entire surface of lower semiconductor substrate 121. Reference numeral 123 denotes an insulating layer formed on thermal oxide layer 122 through a CVD process. Reference numeral 127 denotes an upper semiconductor substrate in which the SOI transistor is formed. The upper semiconductor substrate 127 is a recrystallized silicon layer formed over a portion of insulating layer 123. Here, the recrystallized silicon layer is formed by a recrystallizing process using a laser beam to improve the electrical characteristics of the resulting SOI transistor. Reference numerals 129 and 130 denote field oxide layers for isolating devices. Reference numerals 131 and 132 denote a pad oxide layer and a pad nitride layer, respectively, which define active regions in which the respective transistors are formed following formation of field oxide layers 129 and 130. With this structure, and using the method set forth in U.S. Pat. No. 4,889,829, it is possible to form a bulk transistor and a SOI transistor together on a single substrate.
Unfortunately, this conventional method of manufacturing a semiconductor substrate has its problems. For example, this method requires that the SOI transistor be formed in a recrystallized silicon layer. The presence of the recrystallized silicon layer causes problems in terms of leakage current and contact resistance, as compared with a bulk transistor.